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Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

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17 Author(s)

In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lgmin meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.

Published in:

VLSI Technology, 2008 Symposium on

Date of Conference:

17-19 June 2008