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Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

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11 Author(s)
H. Aikawa ; Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation Semiconductor Company, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan ; E. Morifuji ; T. Sanuki ; T. Sawada
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Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries.

Published in:

2008 Symposium on VLSI Technology

Date of Conference:

17-19 June 2008