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A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

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46 Author(s)
Chen, X. ; IBM Semicond. R&D Center (SRDC), Hopewell Junction, NY ; Samavedam, S. ; Narayanan, V. ; Stein, K.
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For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

Published in:

VLSI Technology, 2008 Symposium on

Date of Conference:

17-19 June 2008