Low VT metal-gate/high-k nMOSFETs — PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions

This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-V
_T
nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The DeltaV
_T
relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar V
_T
tune-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta
₂
C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.