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Compaction on the torus [VLSI layout]

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2 Author(s)
K. Mehlhorn ; Dept. of Comput. Sci., Univ. of Saarlandes, Saarbrucken, West Germany ; W. Rulling

A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area. An effective compaction system frees the designer from the details of the design rules, and hence, increases his or her productivity and on the other hand produces high quality layouts. A general framework for compaction on a torus is introduced. This problem comes up whenever an array of identical cells has to compacted. The framework is instantiated by several specific compaction algorithms: one-dimensional compaction without and with automatic job insertion and two-dimensional compaction

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:9 ,  Issue: 4 )