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Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications

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4 Author(s)
Meng-Hsueh Chiang ; Dept. of Electron. Eng., Nat. Ilan Univ., I-Lan ; Jeng-Nan Lin ; Keunwoo Kim ; Ching-Te Chuang

Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical polysilicon gates. CMOS-compatible 's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.

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Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 9 )