By Topic

A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
10 Author(s)
Chen, Y.H. ; DTP, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu ; Chan, W.M. ; Chou, S.Y. ; Liao, H.J.
more authors

A 0.6 V 45 nm dual-rail SRAM design utilizing an adaptive voltage regulator targeting for an SRAM compiler application is proposed for the first time. The proposed work describes an adaptive mechanism to generate a cell-Vdd (CVDD), which tracks a certain voltage offset with respect to logic-Vdd (VDD), and provides a mean to lower the VDD down to 0.6 V. To relax IR-drop constraints of CVDD power routings in P&R flow, shifting bite-line (BL) pre-charge power supply from CVDD to VDD is adopted in this work. This also avoids the congestion of the VDD and CVDD power mesh. A 45 nm test chip has demonstrated that these concepts successfully can push the VDD_min down to 0.6 V, which is > 250 mV lower than the conventional single-rail SRAMpsilas.

Published in:

VLSI Circuits, 2008 IEEE Symposium on

Date of Conference:

18-20 June 2008