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A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication

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10 Author(s)
Pozzoni, M. ; STMicroelectronics, Pavia ; Erba, S. ; Viola, P. ; Pisati, M.
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A 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3 mm2 and consumes 140 mA from 1 V at 8.5 Gb/s.

Published in:

VLSI Circuits, 2008 IEEE Symposium on

Date of Conference:

18-20 June 2008