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Experimental evaluation of digital-circuit susceptibility to voltage variation in dynamic frequency scaling

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5 Author(s)

Logical operations in CMOS digital integration are highly prone to fail as the amount of power-supply (PS) drop approaches to threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, in relation with instruction- level programming for logical failure analysis. Experimental measurements demonstrate that the increased susceptibility of processor operation with dynamic frequency scaling (DFS) can be mitigated through PS noise shaping.

Published in:

2008 IEEE Symposium on VLSI Circuits

Date of Conference:

18-20 June 2008