A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers

A digital near-end crosstalk (NEXT) canceller merged with an analog equalizer for multi-lane serial-link receivers has been realized in 0.13mum CMOS technology. With the proposed sign-sign block least-mean-square (SSB-LMS) circuit, a 5 Gb/s PRBS of 231
^mnplus1
suffered from both the channel loss and NEXT for 10-inch FR4 traces is successfully equalized. The measured BER is 10
^-12
and the measured maximum peak-to-peak jitter is 49.7 ps. This chip occupies 0.56times0.76 mm
²
and consumes 177 mW including buffers from a 1.2 V supply.