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A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

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15 Author(s)
Nazemi, A. ; ClariPhy Commun., Inc., Irvine, CA ; Grace, C. ; Lewyn, L. ; Kobeissy, B.
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A 10.3 GS/s ADC with 5 GHz input BW and 6 bit resolution in 90 nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6 dB SNDR) for a 100 MHz input signal and 5.1 ENOB (32.4 dB SNDR) for a 5 GHz input (Nyquist) with phase offset correction across the interleaved array.

Published in:

VLSI Circuits, 2008 IEEE Symposium on

Date of Conference:

18-20 June 2008

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