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Online test and fault-tolerance for nanoelectronic programmable logic arrays

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2 Author(s)
Garcia, S. ; Dept. of Comput. Sci. & Eng., Univ. of California, La Jolla, CA ; Orailoglu, A.

Fault-tolerance is one of the major challenges facing nanoelectronic systems. Previous defect-tolerance techniques have focused on offline testing and are ill-suited for handling device death. We propose a fault-tolerance scheme for nanoelectronic PLAs that is based on checkpointing. With low overhead, our scheme is able to test and diagnose crosspoint faults that may appear in the PLA during its operational lifetime.We also present a new test vector compaction algorithm that significantly reduces the number of test vectors. This new algorithm takes advantage of the density and reconfigurability of nanoelectronic circuits by raising the granularity of defect diagnosis to the row/column level. We are therefore able to reduce the number of test vectors to O(n+p) for a PLA with n input and p product lines without sacrificing diagnosability. Experimental results show that our checkpointing scheme, together with the compaction algorithm, tolerates a much higher fault rate than previously possible.

Published in:

Nanoscale Architectures, 2008. NANOARCH 2008. IEEE International Symposium on

Date of Conference:

12-13 June 2008