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DSP implementation of a Range Azimuth CFAR processor

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2 Author(s)
Magaz, B. ; R&D Center, Algiers ; Bencheikh, M.L.

In this paper, we present DSP architecture for target detection based on range azimuth cell averaging constant false alarm rate (ARCA-CFAR) processor with non coherent integration. The proposed architecture has been designed to deal with parallel processing and to be configured for the RACA-CFAR algorithm implementation. The design has been implemented on a Texas Instruments TMS320C6711 digital signal processor board with a good performance improvement. The proposed system scheme and the real time implementation results are presented and discussed in this paper.

Published in:

Radar Symposium, 2008 International

Date of Conference:

21-23 May 2008

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