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SystemC-based Reconfigurable IP Modelling for System-on-Chip Design

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4 Author(s)
Ahmadinia, A. ; Sch. of Eng. & Electron., Univ. of Edinburgh, Edinburgh ; Ahmad, B. ; Erdogan, A. ; Arslan, T.

A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer'sA new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and plugged into a LEON platform for co-simulation. productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and plugged into a LEON platform for co-simulation.

Published in:

Adaptive Hardware and Systems, 2008. AHS '08. NASA/ESA Conference on

Date of Conference:

22-25 June 2008

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