TLM Platform Based on SystemC for STARSoC Design Space Exploration

The increasing complexity of embedded systems imposes system designers to use higher levels of abstraction than RTL in order to model, validate and analyze a system performances. It permits to prevent costly redesign efforts at RTL, which can adversely affect time-to-market. For this purpose transaction level modeling (TLM) approach is used. It allows the designers to rapidly verify and develop their designs at earlier design stages. In this paper we define the methodology we used to construct the STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-On-Chip) TLM simulation environment. This platform aims to provide a rapid and accurate design space exploration at higher levels of abstractions for multiprocessor system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. In order to assist the system designer to find the best MPSoC solution depending on the application, we used SystemC language for modeling and simulating the design. The platform includes models for OpenRISC ISSs, bus model based on wishbone protocol and memory models. The simulation is based on different high level of abstractions.