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In this paper a formalized methodology is presented for mapping behavioral DSP kernels onto a novel reconfigurable architectural template. The architectural template is generated by a design technique called flexibility inlining, which delivers high performance coarse-grained reconfigurable architectures. The proposed methodology enables a seamless flow from high level specification to RTL implementation. A specialized intermediate representation model and a set of mapping algorithms have been considered to exploit the structure of the targeted architectures. Experimental results on DSP benchmark applications proves the efficiency of the proposed approach comparing with reconfigurable datapaths composed by standard coarse-grained cells.