Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Xydis, S. ; Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens ; Economakos, G. ; Soudris, D. ; Pekmestzi, K.

In this paper a formalized methodology is presented for mapping behavioral DSP kernels onto a novel reconfigurable architectural template. The architectural template is generated by a design technique called flexibility inlining, which delivers high performance coarse-grained reconfigurable architectures. The proposed methodology enables a seamless flow from high level specification to RTL implementation. A specialized intermediate representation model and a set of mapping algorithms have been considered to exploit the structure of the targeted architectures. Experimental results on DSP benchmark applications proves the efficiency of the proposed approach comparing with reconfigurable datapaths composed by standard coarse-grained cells.

Published in:

Adaptive Hardware and Systems, 2008. AHS '08. NASA/ESA Conference on

Date of Conference:

22-25 June 2008