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SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications

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4 Author(s)
Osterloh, B. ; IDA, Tech. Univ. Braunschweig, Braunschweig ; Michalik, H. ; Fiethe, B. ; Kotarowski, K.

Configurable system-on-chip (SoC) solutions based on state-of-the art FPGA have successfully demonstrated flexibility and reliability for scientific space applications like the Venus Express mission. Future high end payload applications (e.g. Solar Orbiter) demand high-performance on-board processing because of the discrepancy between extreme high data volume and low downlink channel capacity. Furthermore, in-flight reconfiguration ability enhances the system with re-programmable hardware and thus a maintenance potential. To achieve these advanced design goals a reconfigurable system-on-chip (RSoC) architecture is proposed supported by a flexible communication architecture. The flexibility for on-chip communication is covered by a dedicated network-on-chip (NoC) approach. The configurable system-on-chip solution is introduced and the advantages are outlined. Additionally we present our newly developed NoC approach, system-on-chip wire (SoCWire) and outline its performance and the applicability for in-flight reconfigurable systems.

Published in:

Adaptive Hardware and Systems, 2008. AHS '08. NASA/ESA Conference on

Date of Conference:

22-25 June 2008

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