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A CMOS neural network for pattern association

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3 Author(s)
Walker, M. ; Arizona State Univ., Tempe, AZ, USA ; Hasler, P. ; Akers, L.A.

The authors present an analog complementary metal-oxide semiconductor (CMOS) version of a model for pattern association, along with discussions of design philosophy, electrical results, and a chip architecture for a 512-element, feed-forward IC. They discuss hardware implementations of neural networks and the effect of limited interconnections. They then examine network design, processor-element design, and system operation.<>

Published in:

Micro, IEEE  (Volume:9 ,  Issue: 5 )

Date of Publication:

Oct. 1989

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