By Topic

Iterative decoding of parallel concatenated block codes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Belkasmi, M. ; ENSIAS, Rabat ; Farchane, A.

Parallel concatenated block (PCB) codes based on two systematic block codes and an interleaver are considered. In this study BCH codes are used as component codes. At the reception an iterative decoder using Chase-Pyndiah as soft-in soft-out algorithm is designed. The effects of various component codes, interleaver size and pattern, and the number of iterations are investigated using simulations. The simulation results show that the slope of curves and coding gain are improved by increasing the number of iterations and/or the interleaver size. From the simulations we observe that the codes PCB based on BCH(127,106,7) and BCH(255,215,11) codes are respectively 1.7 dB and 2.1 dB from Shannon limit.

Published in:

Computer and Communication Engineering, 2008. ICCCE 2008. International Conference on

Date of Conference:

13-15 May 2008