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Iterative decoding of parallel concatenated block codes

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2 Author(s)
Mostafa Belkasmi ; ENSIAS, Rabat, Morocco ; Abderrazak Farchane

Parallel concatenated block (PCB) codes based on two systematic block codes and an interleaver are considered. In this study BCH codes are used as component codes. At the reception an iterative decoder using Chase-Pyndiah as soft-in soft-out algorithm is designed. The effects of various component codes, interleaver size and pattern, and the number of iterations are investigated using simulations. The simulation results show that the slope of curves and coding gain are improved by increasing the number of iterations and/or the interleaver size. From the simulations we observe that the codes PCB based on BCH(127,106,7) and BCH(255,215,11) codes are respectively 1.7 dB and 2.1 dB from Shannon limit.

Published in:

Computer and Communication Engineering, 2008. ICCCE 2008. International Conference on

Date of Conference:

13-15 May 2008