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An FPGA architecture for CABAC decoding in manycore systems

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2 Author(s)
Roberto R. Osorio ; University of Santiago de Compostela, Dept. Electronics and Computer Science, Spain ; Javier D. Bruguera

Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arithmetic decoding (AD) in H.264 video coding standard is a sequential task that takes a significant part of computing time. In present and future multicore and manycore systems, AD becomes a bottleneck as it cannot be parallelized, limiting the concurrent execution of other tasks. In this paper, an FPGA-based accelerator is proposed to speed-up AD in H.264 and enable parallel decoding at macroblock and frame levels scaling up to tens or hundreds of cores.

Published in:

2008 International Conference on Application-Specific Systems, Architectures and Processors

Date of Conference:

2-4 July 2008