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Fast custom instruction identification by convex subgraph enumeration

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5 Author(s)
Atasu, K. ; Dept. of Comput., Imperial Coll. London, London ; Mencer, O. ; Luk, W. ; Ozturan, C.
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Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and silicon area combinations. This work introduces a novel method for adapting the instruction set to match an application captured in a high-level language. A simplified model is used to find the optimal instructions via enumeration of maximal convex subgraphs of application data flow graphs (DFGs). Our experiments involving a set of multimedia and cryptography benchmarks show that an order of magnitude performance improvement can be achieved using only a limited amount of hardware resources. In most cases, our algorithm takes less than a second to execute.

Published in:

Application-Specific Systems, Architectures and Processors, 2008. ASAP 2008. International Conference on

Date of Conference:

2-4 July 2008