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On-chip communication architecture plays an important role in determining the overall performance of the system-on-chip (SoC) design. In the recourse sharing mechanism of SoC, the communication architecture should be flexible to offer high performance over a wide range of traffic. Conventional SoC architecture typically employ priority or time division multiple access (TDMA) based communication architecture. However, these techniques are often in adequate. In the former, low priority components may suffer from starvation, while high priority components may have large latency. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. In this paper dynamic lottery bus arbiter architecture for a system on chip is discussed. The architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method. The architecture is model in VHDL and some of the simulation results are presented.