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Design and VLSI implementation of a Low Probability of Error Viterbi Decoder

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2 Author(s)
C. Arun ; Dept. of Inf. Technol., Venkateswara Coll. of Eng., Chennai ; V. Rajamani

The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital wireless communication channels, enabling reliable transmission to be achieved over noisy and fading channels. In this paper a novel approach to design a high throughput with reduced bit error probability Viterbi decoder is described and implemented. Low bit error rate (BER) can be achieved by increasing the free distance (dfree) of the Viterbi decoder without increasing complexity. The increase in dfree has been achieved by a proposed non-polynomial convolutional code method. A decoder system with code rate of k/n=frac14, constrain length K=3 has been implemented on Xilinx Spartan-III. The performance of viterbi decoder with the proposed method has been improved from 27% to 75% of errors are detected and corrected. We have also achieved a high speed (84.958 Mbps) and low Bit Error Rate (BER) viterbi decoder. Experimental results shows that the proposed viterbi decoder provides satisfactory Pe performance and high operating speed under various conditions including AWGN, co-channel interference and adjacent channel interference environments.

Published in:

2008 First International Conference on Emerging Trends in Engineering and Technology

Date of Conference:

16-18 July 2008