Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Data memory management in partial dynamically reconfigurable systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Montone, A. ; DEI, Politec. di Milano, Milan ; Rana, V. ; Santambrogio, M.D.

This paper aims at introducing a novel approach for the management of processor data memory in reconfigurable systems. The proposed approach allows the individual management of separated data and the dynamic update of the memory with a partial bitstream. By following this way it is possible to create a system in which several master components (e.g., soft-processors or hard-processors) can be dynamically configured and in which their memory can be dynamically changed. In the first section the reconfigurable scenario and its problems concerning to memory management will be introduced. The following sections will describe the state of the art and the development details of the tool that implements the proposed approach. Finally, a set of experimental results will be presented and conclusive remarks will be drawn.

Published in:

Industrial and Information Systems, 2007. ICIIS 2007. International Conference on

Date of Conference:

9-11 Aug. 2007