By Topic

Mechanism and Improvement of On-Resistance Degradation Induced by Avalanche Breakdown in Lateral DMOS Transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Chen, J.F. ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan ; Lee, J.R. ; Kuo-Ming Wu ; Huang, Tsung-Yi
more authors

On-resistance (Ron) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. Ron degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in Ron degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced Ron degradation.

Published in:

Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 8 )