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Power Reduction Techniques for LDPC Decoders

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3 Author(s)
Darabiha, A. ; Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON ; Carusone, A.C. ; Kschischang, F.R.

This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders amenable to low-voltage and low-power operation. First, a highly-parallel decoder architecture with low routing overhead is described. Second, we propose an efficient method to detect early convergence of the iterative decoder and terminate the computations, thereby reducing dynamic power. We report on a bit-serial fully-parallel LDPC decoder fabricated in a 0.13-mum CMOS process and show how the above techniques affect the power consumption. With early termination, the prototype is capable of decoding with 10.4 pJ/bit/iteration, while performing within 3 dB of the Shannon limit at a BER of 10-5 and with 3.3 Gb/s total throughput. If operated from a 0.6 V supply, the energy consumption can be further reduced to 2.7 pJ/bit/iteration while maintaining a total throughput of 648 Mb/s, due to the highly-parallel architecture. To demonstrate the applicability of the proposed architecture for longer codes, we also report on a bit-serial fully-parallel decoder for the (2048, 1723) LDPC code in 10 GBase-T standard synthesized with a 90-nm CMOS library.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 8 )