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Validation of executable application models mapped onto network-on-chip platforms

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7 Author(s)
Maatta, S. ; Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere ; Indrusiak, L.S. ; Ost, L. ; Moller, L.
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Due to the increasing design size, complexity, and heterogeneity of todaypsilas embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous models of computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor network-on-chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.

Published in:

Industrial Embedded Systems, 2008. SIES 2008. International Symposium on

Date of Conference:

11-13 June 2008