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A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

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6 Author(s)
Hamada, N. ; Aizu Univ., Aizuwakamatsu ; Shiga, Y. ; Saito, H. ; Yoneda, T.
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This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.

Published in:

Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on

Date of Conference:

23-27 June 2008