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A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries

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2 Author(s)
Imai, M. ; Res. Center for Adv. Sci. & Technol., Univ. of Tokyo, Tokyo ; Nanya, T.

In this paper, we propose a design method for low-power self-timed combinational circuits and latches based on the 1-out-of-4 encoding method. We propose a 1-out-of-4 latch circuit using standard cell libraries in order to establish a semi-custom low-power self-timed design style. The energy consumption of the proposed circuits is about 18% average smaller than that of conventional dual-rail encoded circuits.

Published in:

Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on

Date of Conference:

23-27 June 2008