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2-D systolic arrays for realization of 2-D convolution

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2 Author(s)
Hon-keung Kwan ; Hong Kong Univ., Hong Kong ; Okullo-Oballa, T.S.

An image is regarded as a 2-D array of pixels and is processed by a 2-D array architecture. The image can be acquired in the usual manner by a raster scan method which produces a 1-D array of pixels at real-time video rates. Two 2-D systolic arrays for a 2-D convolver are presented. They have an architecture which accepts this 1-D array of pixels and processes them in a 2-D array of simple processors. This high degree of parallelism is achieved through matrix-vector formulations of 2-D convolution. One array has a serial input, a serial output, and uses a minimum number of multipliers: the other array has parallel input, parallel output, and is suitable for high-speed processing using slow processing elements. Both arrays are modular with nearest-neighbor communications are are suitable for VLSI implementation. In addition, an algorithm for 2-D convolution that explicitly takes into account the boundary conditions is presented. This feature allows a large image to be partitioned so that each partition may be processed by independent 2-D convolvers. It is then possible to process only a specified section of the image or carry out high-speed parallel processing using as many 2-D convolvers as are available

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Circuits and Systems, IEEE Transactions on  (Volume:37 ,  Issue: 2 )