By Topic

Cycling Effect on the Random Telegraph Noise Instabilities of nor and nand Flash Arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Monzio Compagnoni, C. ; Dipt. di Elettron. e Inf., Politec. di Milano, Milan ; Spinelli, A.S. ; Beltrami, S. ; Bonanomi, M.
more authors

The impact of program/erase (P/E) cycling on the random telegraph noise (RTN) threshold voltage instability of NOR and NAND flash memories is studied in detail. RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies.

Published in:

Electron Device Letters, IEEE  (Volume:29 ,  Issue: 8 )