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This paper presents an experimental study of substrate noise isolation in BF-Moat and P+/DT/n-well/DT/P+ guard-ring-defined regions on a lightly doped substrate in the IBM 0.18-mum 7WL bipolar CMOS (BiCMOS) technology. Measurements of substrate noise voltage intentionally generated by an RF power amplifier and 64 digital pad drivers placed on the chip were taken at ten locations throughout the chip, using a capacitively coupled BiCMOS differential sensor circuit. The data show that both isolation structures exhibit effective ability to block out substrate noise for frequencies up to 2-3 GHz. Peak induced substrate noise voltage within the ldquoquiet regionsrdquo was lower by 12-15 dB from that outside the quiet areas.