By Topic

32nm technology node Double-Gate SOI MOSFET using SiO2 gate stacks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Sangiorgi, E. ; ARCES, Univ. of Bologna, Bologna ; Barin, N. ; Braccioli, M. ; Fiegna, C.

State of the art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the Ultra-Thin Silicon Body Double-Gate (UTB-DG) MOSFET. n-MOSFETs designed according to an original scaling strategy are simulated and the main figures of merit of the high-performance MOS transistor for digital applications are evaluated and compared to the requirements of the International Technology Roadmap for Semiconductors.The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field.

Published in:

Nano CMOS, 2006 International Workshop on

Date of Conference:

Jan. 30 2006-Feb. 1 2006