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Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer

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6 Author(s)
Wei Han ; School of Engineering and Electronics, University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, UK. Tel: (+44)131 650 5619 Email: ; Ying Yi ; Mark Muir ; Ioannis Nousias
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Wireless internet access technologies have significant market potential, especially the WiMAX protocol which can offer data rate of tens of Mbps. A significant demand for embedded high performance WiMAX solutions is forcing designers to seek single-chip multiprocessor or multi-core systems that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be strong candidates for future high performance multi-core processor systems. This paper presents several new single-chip multi-core architectures, based on newly emerging dynamically reconfigurable processor cores, for the WiMAX physical layer. A simulation platform is proposed in order to explore and implement various multi-core solutions combining different memory architectures and task partitioning schemes. The paper describes the architectures, the simulation environment, and demonstrates that up to 4.2x speedup can be achieved by employing four dynamically reconfigurable processor cores with individual local memory units.

Published in:

Application Specific Processors, 2008. SASP 2008. Symposium on

Date of Conference:

8-9 June 2008