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System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis

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3 Author(s)
Po-Kuan Huang ; Electrical and Computer Engineering, University of California, Davis, CA 95616, USA. pohuang@ucdavis.edu ; Matin Hashemi ; Soheil Ghiasi

We present a framework for development of streaming applications as concurrent software modules running on multi-processors system-on-chips (MPSoC). We propose an iterative design space exploration mechanism to customize MPSoC architecture for given applications. Central to the exploration engine is our system-level performance estimation methodology, that both quickly and accurately determine quality of candidate architectures. We implemented a number of streaming applications on candidate architectures that were emulated on an FPGA. Hardware measurements show that our system-level performance estimation method incurs only 15% error in predicting application throughput. More importantly, it always correctly guides design space exploration by achieving 100% fidelity in quality-ranking candidate architectures. Compared to behavioral simulation of compiled code, our system-level estimator runs more than 12 times faster, and requires 7 times less memory.

Published in:

Application Specific Processors, 2008. SASP 2008. Symposium on

Date of Conference:

8-9 June 2008