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Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor

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3 Author(s)
Alexandros Papakonstantinou ; Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign. ; Deming Chen ; Wne-Mei Hwu

Different approaches have been proposed over the years for automatically transforming high-level-languages (HLL) descriptions of applications into custom hardware implementations. Most of these approaches however are confined by basic block level parallelism described within the CDFGs (control-data flow graphs). In this work we propose a new high-level synthesis flow which can leverage instruction-level parallelism (ILP) beyond the boundary of the basic blocks. We extract statistical parallelism from the applications through the use of Superblocks and Hyperblocks formed by advanced front-end compilation techniques. The output of the front-end compilation is then used in our high-level synthesis in order to map the application onto a new domain-specific architecture named EPOS (explicitly parallel operations system). EPOS is a stylized micro-code driven processor equipped with novel architectural features that help take advantage of the instruction-level parallelism generated in the front-end compilation. A novel forwarding-path optimization engine is also employed during the high-level synthesis flow in order to minimize the long interconnection wires and the multiplexers in the processor. To evaluate the EPOS processor, we compare its performance with a previous domain-specific processor NISC on a common set of benchmarks. Experimental results show that significant performance gain (3.45times on average) is obtained compared to NISC.

Published in:

Application Specific Processors, 2008. SASP 2008. Symposium on

Date of Conference:

8-9 June 2008