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A speed independent circuit has the property that the relative speed of operation of the various logic elements does not affect the over-all behavior of the circuit. Such circuits have properties which are of particular importance in the design of reliable asynchronous circuits. An Arithmetic Control for a digital computer is one type of logic which can profitably use these characteristics. The design objective established for the Arithmetic Control for the new Illinois computer was to obtain speed-independent operation. This design effort was not completely successful since a small portion of the logic in this control cannot be considered speed-independent unless an assumption is made which is not justified in practice. Using this fact as motivation, these studies investigate three new methods for designing speed-independent logic. In these studies, two very different approaches to the design of control logic are used. The first method is based on a building-block technique where a control logic is formed by properly interconnecting standard subsections of speed-independent logic. When the second technique is used, the sequencing problem is represented by Gray Code movements on an n-cube; these sequencing movements are determined by the mapping of flow chart requirements onto the n-cube. Since the controls designed using these very differents methods were only slightly different in size, it was concluded that within the context of these studies the choice of design method has only a small effect on control size.