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A Low-Jitter Polyphase-Filter-Based Frequency Multiplier With Phase Error Calibration

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2 Author(s)
J. K. Yin ; Inst. for Infocomm Res., Singapore ; P. K. Chan

A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static phase error of the calibration circuit is 2.4 ps. The calibration leads to the normalized rms jitter of 0.049%.

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:55 ,  Issue: 7 )