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In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of 1 GHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200 MHz, while consuming only 60 mW of power. The measured INL and DNL are within plusmn0.7LSB, plusmn0.5LSB, respectively. The measured SNDR is 33.64 dB, when Fin=100 MHz at Fs=1 GHz. The active chip occupies an area of 0.27 mm2 in 0.18 mum CMOS technology.
Date of Conference: 2-4 June 2008