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Design and Synthesis of a High-Speed Hardware Linked-List for Digital Image Processing

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5 Author(s)

To deal with the problem of maintaining variable data set in digital image processing, this paper brings forward a general hardware structure for linked-list. It is designed to accomplish the commonly used functions and some more complicated functions of the linked-list data structure. In order to fully utilize the limited memory resources in embedded hardware platform, we propose a memory recycle scheme to reuse the memory space where the data have been deleted. In our work, the length of the linked-list is parameterized and can be reconfigured. The structure is mapped onto an FPGA chip. Experimental results show that our proposal works functionally well. Only few hardware resources are used and it consumes pretty low power. According to the length of the list, clock speed from 100MHzup to 200MHz is achieved. Compared with the software linked-list structure in PC, our proposal in FPGA achieves 170.4 times of speedup in average. Our design has been utilized into people tracking system successfully.

Published in:

Image and Signal Processing, 2008. CISP '08. Congress on  (Volume:4 )

Date of Conference:

27-30 May 2008