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There are many economic and technical arguments for the reduction of the number of Electronic Control Units (ECUs) aboard a car. One of the key obstacles to achieve this goal is the limited composability, fault isolation and error containment of todaypsilas single processor architectures. However, significant changes in the chip architecture are taking place in order to manage the synchronization, energy dissipation, and fault-handling requirements of emerging billion transistor SoCs (systems-on-a-chip). The single processor architecture is replacing by multi-core SoCs that communicate via shared bus. These emerging multi-core SoCs provide an ideal execution environment for the integration of multiple automotive ECUs into a single SoC. This paper proposed a technique for using shared bus among Multi-core. A fuzzy logic arbiter is presents to manage the shared bus. The input as master ECUpsilas request, are fuzzified by using appropriate membership functions, and rules have been defined to increase and distribute evenly the acceptance rate of each core. System is model using VHDL and some simulation results are presented.
Date of Conference: 4-7 May 2008