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Compiling parallel applications to Coarse-Grained Reconfigurable Architectures

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2 Author(s)
Tuhin, M.A.A. ; Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John''s, NL ; Norvell, T.S.

In this paper a novel approach for compiling parallel applications to a target coarse-grained reconfigurable architecture (CGRA) is presented. We have given a formal definition of the compilation problem for the CGRA. The application will be written in HARPO/L, a parallel object oriented language suitable for hardware. HARPO/L is first compiled to a data flow graph (DFG) representation. The remaining compilation steps are a combination of three tasks: scheduling, placement and routing. For compiling cyclic portions of the application, we have adapted a modulo scheduling algorithm: modulo scheduling with integrated register spilling. For scheduling, the nodes of the DFG are ordered using the hypernode reduction modulo scheduling (HRMS) method. The placement and routing is done using the neighborhood relations of the PEs.

Published in:

Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on

Date of Conference:

4-7 May 2008