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Modeling and simulation of multicore multithreaded processor architectures in SystemC

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3 Author(s)
Ma, N. ; Dept. of Electr. & Comput. Eng., Queen''s Univ., Kingston, ON ; Manjikian, N. ; Sudharsanan, S.

This paper describes a transaction-level simulation model of a multicore, multithreaded architecture and the usage of an application model that generates synthetic single-or multi-threaded execution traces to drive the simulation. The transaction-level model is implemented in SystemC. The parameters for the application model are determined from an analysis of an actual application trace so that the synthetic trace has representative behavior. Results are presented from simulations that use the application model for three different multithreaded workload scenarios with varying degrees of data sharing among the threads within each processor core and across all processor cores. The results demonstrate the impact on performance for the different workloads as the number of cores and the number of threads per core are varied.

Published in:

Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on

Date of Conference:

4-7 May 2008

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