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Cost effective reconfigurable architecture for stream processing applications

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3 Author(s)
Valeri Kirischian ; ERSL, Ryerson University, 350 Victoria Street, Toronto, M5B 2K3, Canada ; Vadim Geurkov ; Lev Kirischian

This paper presents an approach for development of cost-effective custom video/image processing systems. The approach utilizes the concept of temporal partitioning of resources in the partially reconfigurable FPGA devices. Paper proposes architecture of the multi-mode video-stream processor with cyclically reconfigurable structure. The cost-effectiveness of the proposed approach has been analyzed on the basis of experiments conducted on multi-mode adaptive reconfigurable system (MARS) platform that was developed for that purpose. The video-processing cores associated with stereo-vision algorithms have been developed, tested and analyzed. The experiments have shown that the cost-effectiveness of the systems based on proposed approach can be better than the traditional approaches based on large statically configured FPGAs.

Published in:

Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on

Date of Conference:

4-7 May 2008