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Power aware design of superscalar architecture for high performance DSP operations

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3 Author(s)
Ahmed, R. ; Dept. of Comput. Sci. & Eng., Lahore Univ. of Manage. Sci., Lahore ; Sheikh, F. ; Masud, S.

In this paper a methodology for architectural level power optimization of a superscalar processor is proposed. The optimization is targeted at high performance real-time DSP operations. Sample rate conversion operation in software defined radios has been taken as an exemplar operation. Various superscalar configurations have been obtained through a systematic procedure. SimpleScalar architecture modeling tool has been used for simulation along with its power estimation extension - Wattch. Overall performance gain of more than 100 percent has been achieved while meeting all operating constraints.

Published in:

Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on

Date of Conference:

4-7 May 2008

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