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This paper presents an FPGA implementation of the vector SISO algorithm for the (64, 57) extended Hamming code (EH) and (64, 51) extended Bose, Chaudhri, and Hocquenghem code (EBCH). The decoder architecture is defined in VHDL and the circuit is implemented on a Xilinx XC2VP100-1704ff-5 FPGA device. To achieve the required throughput, a pipelined data path architecture operating off a master clock was selected. To reduce gate count, the dynamic range of intermediate results was limited through use of saturation arithmetic. The decoder functionality was verified by means of a test bench that compared the decoded bit stream with error free transmitted signals. SISO decoder design choices that impact the bit error rate (BER) are also presented.