Scheduled System Maintenance:
On May 6th, system maintenance will take place from 8:00 AM - 12:00 PM ET (12:00 - 16:00 UTC). During this time, there may be intermittent impact on performance. We apologize for the inconvenience.
By Topic

FPGA implementation of variants of min-sum algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Tolouei, S. ; Dept. of Syst. & Comput. Eng., Carleton Univ., Ottawa, ON ; Banihashemi, A.H.

This paper presents the FPGA implementation of a number of popular decoding algorithms for a regular rate-1/2 low density parity check code with block length 504 bits. The so-called min-sum (MS) algorithm and two of its variants, known as MS with successive relaxation (SR-MS) and MS with unconditional correction (MS-UC), are implemented. We implement the algorithms on a Xilinx XC2VP100 FPGA device with 4-bit quantization. We show that for MS-UC, the circuit utilization increases by about 2% compared to standard MS and that the throughput is the same as that of MS. For SR-MS, the device utilization is increased by about 26% and the throughput is decreased by approximately 20% compared to standard MS. While the throughput and the area and power consumption of our implementation is comparable to the most recent FPGA implementations of LDPC decoders, ours is the first attempt at implementing an iterative decoding algorithm with memory (SR-MS).

Published in:

Communications, 2008 24th Biennial Symposium on

Date of Conference:

24-26 June 2008