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In this paper the design flow of a 60 GHz LNA in a standard CMOS SOI technology is described. First the 60 GHz band opportunities for very high data rate (multi Gbit/sec) wireless communication systems is presented. Then the paper showed the modeling approach for transmission lines as well as for transistors. Passive elements are modeled with the help of HFSS 3D electromagnetic simulator, whilst the transistors use an empirical high frequency oriented CMOS model. A brief description of a 60 GHz transceiver is given.