Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application

High-resistivity substrate with beyond 1000 ohm-cm realizes high performance in terms of inductor, antenna, MIM capacitor and substrate noise for high- frequency applications. However, this wafer has serious problems for mixed-signal, RF and digital circuits. Those are reduction of high resistivity during sinter process such as 400degC, larger leakage current between nwells, extreme lower snap-back voltage in latch-up behavior and higher RF noise. The RF noise is proportional to square root of Si substrate resistivity in our experience. In this paper, it is shown that these problems can be resolved by the optimum wafer fabrication process and the additional ion implantation.